| 00:14.25 | MonMotha | RobotGuy: yes, why? |
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| 01:35.36 | landley | Has anybody played with http://www.deviceguru.com/ethernet-connector-contains-linux-server/ yet? |
| 01:55.05 | g1powermac_PB | no, but I'd like to play with one |
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| 02:17.28 | ds2 | wonder how well does a cobler get paid... |
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| 09:33.11 | keesj | doing it with a flyswatter is a very attractive idea |
| 09:43.01 | keesj | I guess that would be using the async bitbang interface |
| 09:43.15 | landley | keesj: ok, those last two lines out of context? |
| 09:43.20 | landley | Probably _far_ dirtier than you intended. |
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| 09:49.15 | keesj | I was reading the backlog :P , I asked about a cheap logic analyzer |
| 09:53.14 | keesj | mainly for serial/spi/i2c |
| 09:53.42 | keesj | landley: lol |
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| 18:55.09 | keesj | is trying to use the flyswatter as logic analizer like prpplague suggested :p |
| 19:10.20 | keesj | I think I will only be able to use 2 perhaps 3 lines due to the voltage converters |
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| 21:21.19 | JohnnyL | hi |
| 21:31.00 | keesj | hi |
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| 21:57.19 | keesj | hmm initial test using the flyswatter a logic logger gives me about one sample every 2 ms (500 sample / second) |
| 21:57.28 | keesj | would that be usefull ? |
| 21:58.45 | keesj | here is a (gnu)plot http://box.mmapps.net/flylogger_2008_11_15.png |
| 22:14.26 | MonMotha | keesj: 500Hz is a pretty useless logic analyzer |
| 22:14.36 | MonMotha | how much timing jitter is there? |
| 22:14.36 | keesj | I guess I would need to find a way to use the internal buffer of the chip, |
| 22:14.48 | keesj | No idea |
| 22:14.51 | MonMotha | also is there any channel-channel skew? |
| 22:15.38 | MonMotha | I usually expect at least a MHz or two out of a pretty cheap logic analyzer |
| 22:15.39 | keesj | No , as I have only one channel ATM . but yes , I can only read 8 channels at a time and there are 16 |
| 22:16.21 | MonMotha | A common way to build one on the cheap is to use an FPGA to sample and chuck everything into an internal BRAM based FIFO, then clock it out in chunks something can manage |
| 22:16.30 | MonMotha | that lets you do burst samples at really high rates of speed |
| 22:16.40 | MonMotha | but you're limited by the FPGA's internal block RAM |
| 22:16.51 | MonMotha | higher end designs then chuck it into external SDRAM or similar |
| 22:17.20 | keesj | I indeed saw some open source fpga based things (searching atm) |
| 22:17.42 | MonMotha | nice part about an FPGA is that you can pretty much make it as wide as you'll practically need |
| 22:17.51 | MonMotha | need a 128+ channel setup? OK |
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| 22:20.02 | keesj | http://flash-plaice.wikispaces.com/ this was the one I found , I don't know how alive the probject is |
| 22:20.51 | MonMotha | heh, you don't really need much of a project to pull this off |
| 22:20.59 | MonMotha | grab a Nexys 2 and go to town |
| 22:21.02 | MonMotha | they're $100 |
| 22:21.07 | MonMotha | and they have USB 2.0 for data transfer |
| 22:21.36 | MonMotha | the FPGA configuraiton to do this is pretty simple. Hardest part is the dual port FIFO, and you can grab that from opencores |
| 22:23.26 | keesj | thanks for the tips. but it sounds like fun to try something out with FPGA. |
| 22:25.03 | MonMotha | FPGAs are in general fun :) |
| 22:25.35 | keesj | time to sleep , thanks |
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| 22:29.06 | JoeLlama | what is a good FPGA board for learning on? Meaning low cost and easy to program etc... |
| 22:29.44 | MonMotha | JoeLlama: Digilent Nexys 2 |
| 22:29.56 | MonMotha | $100 and free dev software that runs on Linux |
| 22:30.07 | MonMotha | though I'd pay the (IIRC) $20 for the larger FPGA option |
| 22:30.53 | JoeLlama | unfortunately my development platform is windows |
| 22:31.55 | JoeLlama | looks like a nice board MonMotha |
| 22:32.58 | JoeLlama | http://www.digilentinc.com/Data/Products/NEXYS/Nexys_rm.pdf |
| 22:34.50 | JoeLlama | MonMotha :) |
| 22:36.18 | JoeLlama | MonMotha it also runs under winblows |
| 22:40.10 | JoeLlama | we lost MonMotha :( |
| 22:58.30 | MonMotha | JoeLlama: yes, the software also runs on Windows |
| 22:58.43 | MonMotha | and you want a Nexys 2, not a Nexys. The original is old and discontinued |
| 22:59.34 | JoeLlama | ok thanks :) |
| 23:00.03 | JoeLlama | I'll run that past some people on EFNet #hwdev and #fpga but it looks good. |
| 23:00.24 | MonMotha | it's basically THE option for your requirements in the Xilinx flavor |
| 23:00.30 | MonMotha | I'm guessing Altera has a similar option |
| 23:00.38 | JoeLlama | and there is a $20 option for the larger array? |
| 23:01.14 | MonMotha | JoeLlama: I tihnk so |
| 23:01.28 | JoeLlama | ok thanks |
| 23:01.46 | JoeLlama | I assume it's programmed over USB? |
| 23:02.04 | JoeLlama | powered by USB? |
| 23:02.43 | JoeLlama | MonMotha |
| 23:03.18 | JoeLlama | o k u r bz |
| 23:03.50 | MonMotha | it is not USB powered |
| 23:03.59 | MonMotha | can potentially draw too much juice |
| 23:04.11 | JoeLlama | yeah but programmed via usb? |
| 23:05.20 | MonMotha | yes |
| 23:05.25 | MonMotha | or you can use an external JTAG cable |
| 23:06.38 | JoeLlama | cool and I see that it can be powered by USB according to the referencew... perhaps the older one couldn't.; |
| 23:07.06 | MonMotha | perhaps |
| 23:07.18 | MonMotha | I actually don't have a Nexys or Nexys 2, so I'm just going from memory |
| 23:07.21 | MonMotha | I have a XUPV2P |
| 23:07.55 | JoeLlama | do you like the xupv2p better? |
| 23:08.19 | MonMotha | well, it's not really in the same league |
| 23:09.05 | JoeLlama | oic... looking at the XUPV2P refernce as we speak |
| 23:09.15 | MonMotha | yeah...it's a lot bigger |
| 23:09.17 | MonMotha | and more expensive |
| 23:09.27 | MonMotha | you get two hard PowerPCs |
| 23:09.30 | JoeLlama | yup |
| 23:09.33 | JoeLlama | wow |
| 23:09.40 | JoeLlama | how much is that one? lemme froogle |
| 23:09.59 | MonMotha | you're not likely to find them for sale from resellers, though you may see them on ebay or similar |
| 23:10.02 | JoeLlama | hrm no match |
| 23:10.12 | JoeLlama | how much are they? |
| 23:10.14 | MonMotha | Digilent doesn't sell through resellers |
| 23:10.21 | MonMotha | price should be on their website |
| 23:10.27 | MonMotha | $1600 IIRC unless you're a student |
| 23:11.07 | JoeLlama | wow |
| 23:11.11 | JoeLlama | and for a student? |
| 23:11.17 | MonMotha | I think $300 |
| 23:11.19 | JoeLlama | why are there three power supplies? |
| 23:11.23 | JoeLlama | wow! 300 bux |
| 23:11.25 | MonMotha | which is likely cost or less |
| 23:11.38 | MonMotha | the FPGA itself is $900+ from Digi-Key in qty 1 |
| 23:11.53 | MonMotha | and there are 3 power supplies because there are 3 major rails on the board |
| 23:12.01 | MonMotha | FPGA designs often need 3+ rails |
| 23:12.17 | JoeLlama | ah I see |
| 23:12.27 | MonMotha | usually a VCORE for the FPGA (1.8 or 1.2V in most cases), and then 1-2 I/O voltages (usually 2.5/2.7 and 3.3) |
| 23:12.37 | MonMotha | some designs will also have a 5V rail |
| 23:12.40 | JoeLlama | yeah ok |
| 23:12.49 | JoeLlama | I should start with the first one :) |
| 23:12.58 | MonMotha | I've seen designs with 1.2, 1.8, 2.5, 3.3, and 5V all on one board just for digital stuff |
| 23:13.12 | JoeLlama | I would like to build a show controller (long story) but I think that application is more geared to CPU |
| 23:13.25 | MonMotha | then when you get into mixed signal stuff, you'll end up with dedicated analog supplies that sometimes duplicate voltages; you'll have negative rails, etc. |
| 23:13.41 | MonMotha | most I've ever seen on a board was I think 8 rails |
| 23:13.54 | JoeLlama | http://www.xilinx.com/univ/XUPV2P/Documentation/ug069.pdf <a--- ref manual for that one you mentioned |
| 23:14.47 | MonMotha | Xilinx is pretty good ith docs |
| 23:14.50 | MonMotha | *with |
| 23:15.26 | JoeLlama | what do you use verilog or VDHL? |
| 23:17.09 | MonMotha | I usually use Verilog |
| 23:17.14 | JoeLlama | MonMotha I'm leaning towards verilog |
| 23:17.17 | JoeLlama | cool :) |
| 23:17.21 | MonMotha | I find VHDL to be full of verbose boilerplate that serves almost no purpose |
| 23:17.29 | JoeLlama | yup ok |
| 23:17.41 | JoeLlama | so like does verilog come with that $99 board? |
| 23:17.44 | MonMotha | however, if you're doing a critical piece of design with well spelled out requirements, VHDL will help you be more sure you've met them |
| 23:17.58 | MonMotha | HDL choice is a function of your dev software |
| 23:18.02 | MonMotha | ISE from Xilinx supports both |
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| 23:18.34 | JoeLlama | so the ISE is free then? |
| 23:18.40 | MonMotha | ISE Webpack is |
| 23:19.00 | MonMotha | the full blown ISE which supports the larger devices costs mega $$$, but you don't need it for any of these boards |
| 23:19.13 | JoeLlama | mega bux like how much? |
| 23:19.15 | MonMotha | ISE Webpack 9 even supports the 2VP40, now |
| 23:19.21 | MonMotha | like $3000+, IIRC |
| 23:19.25 | JoeLlama | yeah |
| 23:19.32 | JoeLlama | typical |
| 23:19.33 | MonMotha | I think it might have actually topped $10,000 |
| 23:19.44 | JoeLlama | oh that's too much :) heh |
| 23:19.55 | MonMotha | well, you can use the free one, so that doesn't matter |
| 23:20.24 | JoeLlama | yup :) |
| 23:21.02 | JoeLlama | ok well thanks I'll look at that one board... I think xillinx is the way to go to start huh... |
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