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| 00:37.53 | phaidonx | Hi, I am wrting some piece of code for i2c. I want my LPC21xxx to be working in slave mode so I set I2CONSET to 0x44. This is my first time using this so I just want to know if my train of thought is correct: the arm running the slave code should initialize the ISR, and as long as that's done properly, it's going to eventually get called with a status that says it's being addressed by a master, and the data will be copied to some buffer. So in my main pro |
| 00:38.50 | phaidonx | my issue is I don't know how I can tell that the buffer has "new data" in it since the slave code is not the one initiating the transfer? |
| 01:04.59 | joe_bleau | Won't your slave code see an interrupt when the new data arrives? |
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| 01:41.38 | phaidonx | joe_bleau: yes... so should I like write my own 'protocol' so that say I send a special chain of bits so that I can recognize that I am receiving a new message? |
| 01:43.21 | phaidonx | I mean, I figure the interrupt will be writing data to a buffer, but how do I know that it's not in the process of receiving more bits and that it has received an entire packet? |
| 01:44.13 | phaidonx | oh, the write index! that should go to 0 everytime it starts receiving a new one right? and as long as it's as big as the size of the packet I am expecting that should mean I have a complete packet? |
| 01:44.46 | phaidonx | but then if I try to parse it and the interrupt kicks in because it's receiving more data, that would corrupt it no? |
| 01:45.43 | phaidonx | do I just have to hope that while I am parsing the data I won't receive more ? or is there a better way of doing that? |
| 02:39.09 | joe_bleau | I've not done any IIC slave work. I'd expect the interrupt to fire every time a byte comes in, and |
| 02:39.22 | joe_bleau | it would be up to your code to handle the higher level protocols. |
| 02:40.25 | joe_bleau | My datasheet isn't complete (refers to the 8051 doc), but it also looks like it may flag a start flag as well. |
| 02:43.52 | joe_bleau | Looks like you can read the data register when the SI bit is set, and I'll bet that SI set can trigger an interrupt as well. |
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| 15:24.00 | HKCMD | <PROTECTED> |
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| 15:46.30 | joe_bleau | It would really help troubleshooting if you could make a nice little sketch of the circuit. |
| 15:49.55 | HKCMD | <PROTECTED> |
| 15:50.06 | HKCMD | <PROTECTED> |
| 15:52.38 | HKCMD | <PROTECTED> |
| 15:53.44 | joe_bleau | It's just a popup graphic for me. |
| 15:57.05 | HKCMD | <PROTECTED> |
| 15:58.09 | joe_bleau | I turned on javascript and dug around, but couldn't find a schematic. |
| 15:58.54 | HKCMD | <PROTECTED> |
| 16:00.11 | joe_bleau | Sounds like you need to contact them for support, if they are going to play it that way then. |
| 16:02.21 | HKCMD | ok thanks |
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| 19:22.54 | m4t | any tricks to improve io throughput on a linux 2.6 fpu-less system? |
| 19:23.52 | m4t | my ssd supports udma6, but my promise chip supports like udma2 |
| 19:24.07 | m4t | im getting somewhat low performance via a promise tx4 pci card too |
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