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| 12:17.27 | landley | This place is quiet between 3am and 6am texas time. :) |
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| 19:53.05 | phlyback | <flyback> quick question |
| 19:53.05 | phlyback | <flyback> if I managed to solder up a rom to a juicebox |
| 19:53.06 | phlyback | <flyback> how hard would it be to put like u-boot on it |
| 19:53.08 | phlyback | <flyback> then jump to sd card off the cart slot |
| 19:53.24 | phlyback | because thx to kynar wire, I can actually do some of the smaller stuff |
| 19:53.37 | phlyback | but it's like 48x2 joints I will have to do |
| 19:53.44 | phlyback | so I am not going to try if it's going to be a nightmare |
| 19:53.51 | phlyback | to get the thing jtag'd and ready to roll |
| 19:54.02 | phlyback | all I need is a simple random image application on it |
| 19:55.18 | phlyback | nm |
| 19:55.29 | phlyback | I thought I had a 3.3 flash chip |
| 19:55.34 | phlyback | so much for that idea |
| 19:55.55 | phlyback | anyone played with putting u-boot into a disk-on-chip? |
| 20:00.36 | phlyback | no wait I do have some +3.3 ones hmm |
| 20:00.41 | phlyback | trashes some video cards |
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| 21:51.06 | mrtep | Hi, may I ask about ARM programming here? |
| 21:58.44 | SpeedEvil | sure. It's a bit quiet at the moment |
| 22:01.50 | mrtep | Ok, its about ARM's MMU. Is there a way to dump its memory mapping, so I can get how the virtual addresses translates to physical ones? I have no source code of the current device, just a JTAG connection. |
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| 22:05.27 | SpeedEvil | I know unfortunately little - however isn't the MMU config in RAM? |
| 22:05.44 | roxfan | yes, there is a cp15 register that holds the translation table base |
| 22:06.49 | mrtep | Yes, I can turn off the MMU by clearing its bit on cp15 |
| 22:07.16 | roxfan | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0198e/Babigffd.html |
| 22:07.28 | roxfan | (assuming you have an arm9) |
| 22:07.33 | mrtep | But about getting the virtual layout, get I get it via CP15 also? |
| 22:07.40 | mrtep | Yes, arm9 |
| 22:07.58 | roxfan | as i said, read the translation table base |
| 22:08.03 | roxfan | then read the table itself |
| 22:08.58 | roxfan | http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/Babjcchb.html |
| 22:11.43 | mrtep | Ah, so the table is stored in the RAM itself, not on registers |
| 22:12.02 | roxfan | yes |
| 22:12.11 | mrtep | The registers only contains a pointer to it |
| 22:12.19 | mrtep | Nice |
| 22:13.23 | mrtep | Funny how I missed that very page |
| 22:14.45 | SpeedEvil | Windows on ARM could be interstging from a market POV |
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| 22:18.22 | mrtep | ah yes |
| 22:23.35 | mrtep | hmm, the table's format seems a little bit tricky |
| 22:24.02 | mrtep | I'll spend some time studying that. |
| 22:24.07 | mrtep | thanks :) |
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| 23:27.36 | mrtep | The ARM reference manual says the address of the table is contained in the bits [31:14] of the c2 register. Does that means that only 18 bits are available, forcing the table to reside in the 0x0 - 0x40000 (2^18) range? Did I get that right? |
| 23:28.27 | SpeedEvil | Unless that's shifted |
| 23:28.55 | SpeedEvil | So it can be anywhere in 2^32 at a granularity of 2^12 or so |
| 23:29.08 | SpeedEvil | 14 |
| 23:29.11 | roxfan | it must be aligned, yes |
| 23:29.17 | roxfan | "This base address must be on a 16KB boundary." |
| 23:29.39 | mrtep | Oh yep |
| 23:29.48 | roxfan | basically they ignore the low bits |
| 23:30.33 | mrtep | so, I get the register value, shift right by #14, and multiplies by 16k |
| 23:32.59 | roxfan | which produces the equivalent number :) |
| 23:33.16 | bsdfox_ | shift left? |
| 23:33.30 | bsdfox_ | or are you working on big endian |
| 23:33.37 | mrtep | little |
| 23:34.22 | mrtep | i shifted right to remove the [13:0] bits |
| 23:34.26 | mrtep | is that right? |
| 23:34.39 | bsdfox_ | wouldn't you want to shift left by 14 to multiply by 16k? |
| 23:34.52 | bsdfox_ | yeah |
| 23:35.05 | mrtep | ah yeah |
| 23:35.30 | mrtep | it produces the same thing |
| 23:35.43 | mrtep | just doing step by step to get it clear |
| 23:35.44 | mrtep | heh |
| 23:35.55 | roxfan | <roxfan> basically they ignore the low bits |
| 23:41.36 | mrtep | hmm, the contents of the address are all zero. |
| 23:42.24 | mrtep | and the table wouldn't be on 0x0, there are code on there, the vectors |
| 23:42.45 | mrtep | strange, i'm probably doing something wrong |
| 23:44.24 | roxfan | you sure you got the right reg? |
| 23:45.23 | mrtep | MRC p15, 0, r0, c2, c0, 0 #(c2, right?) |
| 23:45.40 | roxfan | yeah looks correct |
| 23:45.49 | roxfan | maybe mmu isn't on? |
| 23:46.07 | mrtep | I'm in supervisor mode |
| 23:46.21 | mrtep | openocd tells me its enabled |
| 23:46.30 | mrtep | let me check c0 |
| 23:47.04 | mrtep | c1, I mean |
| 23:47.31 | mrtep | c1 is 340349, that mean the last bit is 1 = MMU on |
| 23:48.48 | roxfan | weird |
| 23:50.57 | mrtep | yes.. |
| 23:51.01 | roxfan | ah, high vectors are enabled |
| 23:51.10 | roxfan | so maybe it does have tlb at 0? |
| 23:52.00 | mrtep | the initial vector table is at 0xffff0000 |
| 23:52.01 | roxfan | try dumping some bytes |
| 23:52.55 | mrtep | reading address 0 I get data abort on openocd, except if I add the phys flag |
| 23:53.17 | roxfan | well yeah you should read physical memory |
| 23:54.03 | roxfan | hmm i wonder if you can ask openocd to dump tlb |
| 23:55.19 | roxfan | it looks like there is some "lockdown tlb" stuff which might interfere |
| 23:55.31 | mrtep | hmm |
| 23:55.56 | roxfan | http://openocd.sourcearchive.com/documentation/0.4.0-1/arm920t_8c-source.html check arm920t_handle_read_mmu_command |
| 23:56.27 | mrtep | i'll check |
| 23:56.49 | mrtep | 920t only? |
| 23:57.11 | mrtep | mine is 926ej-s, does it apply? |
| 23:57.15 | roxfan | probably |
| 23:57.32 | roxfan | hmm, it seems it has 'read_mmu' command |
| 23:57.34 | roxfan | check it? |
| 23:57.44 | roxfan | "dump I/D mmu content to file" |
| 23:58.47 | roxfan | ah, 926 target doesn't implement it... |
| 23:59.07 | mrtep | :( |