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| 13:57.01 | keesj | I am trying to understand the encoding of the branch instruction on ARM |
| 13:58.10 | keesj | they talk about imm24 (as the encoding for the relative address) |
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| 13:59.41 | keesj | what's that ( I know it is a kind of notation where a part of the bits are used to rotate or shift the rest ) |
| 14:02.58 | keesj | I just wonder what the exact encoding is 0xeafffffe for example has fffffe encoded (and this is most probably -8) |
| 14:03.41 | T0mW | it is relative |
| 14:03.48 | T0mW | not absolute |
| 14:04.06 | T0mW | IIRC |
| 14:04.34 | keesj | (in asm this is b . ) branch to the current address and the exposed PC on arm is ahead of the instruction |
| 14:05.10 | T0mW | all opcodes are single byte, that is why you see loads of immediate values sometimes done as a succession of loads / shifts / ORs. |
| 14:05.19 | T0mW | cache |
| 14:05.54 | T0mW | I think the instruction cache is something like 8 bytes? |
| 14:06.59 | T0mW | so, it has fetched the next instruction (moved the program counter) while executing the "current" opcode. |
| 14:07.33 | T0mW | weird little processor if you are coming over from 8051 / 68HC11 and it doesn't work as expected. |
| 14:08.14 | T0mW | I get the heck out of ARM asm as fast as possible and get into C quickly. heh |
| 14:08.40 | T0mW | keesj: what are you doing, working on one of the bootloaders? |
| 14:09.24 | keesj | http://aelmahmoudy.users.sourceforge.net/electronix/arm/chapter2.htm Branch instructions contain a signed 2's complement 24 bit offset. This is |
| 14:09.27 | keesj | shifted left two bits, sign extended to 32 bits, and added to the PC. |
| 14:09.41 | T0mW | heh |
| 14:09.59 | keesj | <PROTECTED> |
| 14:09.59 | keesj | offset must take account of the prefetch operation, which causes the PC to |
| 14:09.59 | keesj | be 2 words (8 bytes) ahead of the current instruction. |
| 14:10.07 | T0mW | yes |
| 14:10.46 | keesj | I am working on the MINIX arm port and currently trying to crash drivers bij injecting code into them. |
| 14:10.58 | T0mW | when I encountered the ARM for the first time, I wondered why a 32bit processor only limited the chip select (memory regions) to 24 bits... |
| 14:12.07 | T0mW | well, 26 actually. |
| 14:13.02 | keesj | there are other instructions that branch to an address in a register and for other things like coding constants they do some more shifting stuff |
| 14:14.56 | keesj | I guess 25 bits (as the offest can also be negative) |
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| 14:32.55 | keesj | alright so fffffe == -2 in thow's complement notation and that shifted by 2 == -8 |
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| 16:12.47 | landley | The last three times I set down to do my CELF slides, I redid the toybox roadmap, the aboriginal linux about page, and the architectures page, |
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| 16:12.55 | landley | None of which are actually quite _finished_. |
| 16:15.03 | landley | keesj: ooh, pretty web page. |
| 16:16.09 | landley | TOmW: arm started with something like 24,000 transistors total. This has its upsides, and its downsides. |
| 16:18.02 | T0mW | landley: yeah, KISS |
| 16:18.49 | T0mW | Intel adds new opcodes, ARM just lowers the power usage. |
| 16:18.54 | T0mW | and ups the clock. |
| 16:41.21 | landley | T0mW: there's limits to upping the clock, you can increase the cache and go SMP pretty easily. Plus offload stuff on SoC coprocessors. |
| 16:41.33 | landley | But really, you don't need to pipeline if the whole thing is small enough to fit in one stage. |
| 16:41.48 | T0mW | landley: yeah, they then add more cores. More fun for us! |
| 16:42.07 | landley | Optimizations are always circumstantial. |
| 16:42.26 | landley | Don't calculate a value, precompute a table of values! Oh, the calculate-it version runs out of L1 cache and the table is too big for L2? Huh. |
| 16:42.56 | landley | I have watched _that_ particular see-saw go back and forth something like 5 times now, just since I started paying attention. |
| 16:43.38 | landley | Make the cache bigger! Separate l1 and l2 caches... |
| 16:44.15 | landley | I've gotten to the point where I cringe at the phrase "loop unrolling"... |
| 16:44.39 | T0mW | heh |
| 16:44.48 | landley | Decent branch predictor, loop unrolling gets you nothing. |
| 16:45.02 | landley | Except less code fitting in a cache line. |
| 16:45.17 | landley | But as always, there are only two approaches: |
| 16:45.26 | landley | 1) Benchmark it on the hardware you're going to deploy on. |
| 16:45.40 | landley | 2) Do the simple thing, and let Moore's Law do its job. |
| 16:45.53 | landley | I lean pretty strongly towards #2. |
| 16:46.18 | landley | Locality of reference is almost always good, small simple code, fewer cold path accesses... |
| 16:46.32 | landley | Speed of light isn't changing any time soon... |
| 16:46.58 | landley | But optimizations you don't _do_ won't turn into pessimizations to be ripped out later. |
| 16:47.09 | landley | "When in doubt, use brute force." |
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