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| 00:59.03 | SpeedEvil | aojpl: the JTAG bus is generally in hardware |
| 00:59.47 | SpeedEvil | you hook up the JTAG in/out serial pins of all devices in a chain, and the global pins separately |
| 01:00.05 | aojpl | what do you mean by global pins? |
| 01:00.13 | SpeedEvil | the clock |
| 01:00.16 | SpeedEvil | ... |
| 01:01.24 | aojpl | and just with the JTAG pins alone, boundary scanning can be achieved? |
| 01:08.03 | SpeedEvil | you can activate the JTAG bits of each chip. these will generally allow you to (slowly) probe and activate mk oat pins of the chip |
| 01:08.32 | SpeedEvil | so if you have JTAG on the MCU, you can bit-bang programming a flash, for example |
| 01:08.48 | SpeedEvil | bits = core |
| 01:09.34 | aojpl | i see that it can also test for assembly errors |
| 01:10.36 | aojpl | but im not sure how thats implemented - as in what kind of software on the host pc side would be required, and how would it know my schematic |
| 01:13.02 | SpeedEvil | that, I'm less clear on |
| 01:13.36 | aojpl | hmm okay |
| 01:13.49 | SpeedEvil | as I understand it, software typically takes a board definition file, and you can then do stuff with a language typically |
| 01:15.04 | aojpl | i see |
| 01:15.55 | aojpl | there are resources that explain its operation, but not how to actually implement it |
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| 23:09.18 | slashbeast | landley: did you ever managed to get working openssh *static* with uclibc? |
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