| 01:53.23 | *** join/#elinux [mYa]_KiD_Reles (~cd@pD9547B2A.dip.t-dialin.net) |
| 02:05.10 | *** join/#elinux prpplague (~billybob@ppp-70-242-222-65.dsl.rcsntx.swbell.net) |
| 02:05.17 | prpplague | ho ho ho |
| 02:10.07 | prpplague | TimRiker: did you do the jflash mods for tuxscreen? |
| 02:28.01 | *** join/#elinux Skaya (~skaya@ayaks.net2.nerim.net) |
| 02:31.29 | *** join/#elinux T0mW (tom@24.152.249.134.res-cmts.sth.ptd.net) |
| 02:33.13 | prpplague | T0mW: ho ho ho |
| 02:33.54 | T0mW | prpplague: yeah, just doing some crash recovery. Had the power go out, I shut the computers down, but the mythtv box lost its database connectivity somehow. |
| 02:34.28 | prpplague | T0mW: lovely |
| 02:34.38 | prpplague | T0mW: setup some test apps for jtag |
| 02:34.45 | prpplague | T0mW: but something is missing |
| 02:35.12 | prpplague | T0mW: switching direction for the data lines is not working as i would expect |
| 02:36.20 | T0mW | what do yo mean, "switching direction..." |
| 02:38.14 | *** join/#elinux jcrouse (~nobody@vc7-1-203.dsl.netrack.net) |
| 02:40.34 | prpplague | T0mW: the data lines have to be set for either input or output |
| 02:40.52 | prpplague | T0mW: i.e. read/writing |
| 02:41.41 | T0mW | you mean D0..D31 ? |
| 02:42.01 | prpplague | yea |
| 02:42.04 | T0mW | ok |
| 02:42.12 | T0mW | set signal D0 in |
| 02:42.15 | T0mW | set signal D1 in |
| 02:42.18 | T0mW | set signal D2 in |
| 02:42.20 | T0mW | ... |
| 02:42.22 | T0mW | then |
| 02:42.26 | T0mW | shift dr |
| 02:42.33 | T0mW | then |
| 02:42.51 | T0mW | wait |
| 02:43.01 | T0mW | you can do a "peek <address>" |
| 02:43.22 | prpplague | T0mW: hehe, your still talking script stuff from jtag tools |
| 02:43.41 | prpplague | T0mW: i'm doing more low level stuff |
| 02:43.53 | T0mW | well, you need some kind of high level functions or you'll go absolutely nuts. |
| 02:43.56 | prpplague | T0mW: problem is i set the a line like D0 to out |
| 02:44.13 | prpplague | T0mW: then i write a 1 to the D0 out line |
| 02:44.19 | T0mW | follow the code for bus_read() in Jtag/src/bus/lh7a400.c |
| 02:44.21 | prpplague | T0mW: that part is good |
| 02:44.56 | prpplague | T0mW: problem is when i write a 0 to to the D0 out line, the D0 ctrl line goes to input as well |
| 02:45.14 | prpplague | T0mW: hehe, yea, looked it over |
| 02:45.18 | T0mW | well, when you are shifting data out into the TDI input, at each clock, you get a data bit shifted out TDO of the target. |
| 02:45.41 | prpplague | T0mW: right |
| 02:45.52 | prpplague | T0mW: so you have one cycle behind |
| 02:46.04 | T0mW | you capture that string of bits into an array. In the case of the LH7A400, you have 507 bits to shift out and capture in. |
| 02:46.46 | T0mW | when you get the array of bits from TDO (the target), then you refer to the BSDL table to see where to pluck information you want out of which bit. |
| 02:46.48 | prpplague | T0mW: yep |
| 02:46.51 | T0mW | in the bit array. |
| 02:47.09 | prpplague | T0mW: yep |
| 02:47.19 | T0mW | so what's not working? |
| 02:48.33 | prpplague | one sec, youngin got a splinter |
| 02:48.51 | T0mW | for the data bus stuff (D0, D1, D2, ...) there are three bits associated with, say, D0. an input state bit, and output state bit and a control bit which determines the direction of the D0 line at the target (in or out). |
| 02:49.04 | prpplague | T0mW: yep |
| 02:49.18 | prpplague | T0mW: d0_en d0_out d0_in |
| 02:49.22 | T0mW | right |
| 02:49.34 | prpplague | T0mW: when d0_en = 1 then the d0_out works |
| 02:49.52 | T0mW | ... |
| 02:49.53 | *** join/#elinux Skaya (~skaya@ayaks.net2.nerim.net) |
| 02:50.10 | T0mW | not sure of the polarity for an output, but, ok |
| 02:50.23 | prpplague | T0mW: based on the data from the bsdl |
| 02:50.35 | prpplague | T0mW: ok so i set d0_en to 1 |
| 02:50.39 | T0mW | k |
| 02:50.43 | prpplague | T0mW: then i set d0_out to 1 |
| 02:50.46 | prpplague | T0mW: that works |
| 02:50.50 | T0mW | k |
| 02:50.54 | prpplague | T0mW: but...... |
| 02:51.13 | prpplague | T0mW: when i set d0_out to 0 ...... d0_en also goes to 0 |
| 02:51.53 | T0mW | odd, are you sure you're looking at the correct numbered bit? I mean you may be seeing a "reflection" on DB_in ? |
| 02:52.10 | T0mW | s/DB_in/D0_in/ |
| 02:52.24 | prpplague | T0mW: hehe, yep, confirmed it all with the sharp rep and our in house EE |
| 02:52.45 | T0mW | prpplague: very important question: does the D0 go low when you write a zero ? |
| 02:52.47 | prpplague | T0mW: the sharp rep said the same the thing "odd" |
| 02:53.29 | prpplague | T0mW: d0_out does go low when a zero is writen ONLY if d0_en is 1 before the write |
| 02:54.49 | T0mW | ok, so you're saying that the D0_en is not "latched" at the target CPU, that you have to continually "refresh" it? |
| 02:55.06 | prpplague | T0mW: basically yea |
| 02:55.30 | prpplague | T0mW: i wrote a routine to test all the possible combos before i left the office |
| 02:55.37 | T0mW | but, when you write to the port bit, the value at the port STAYS SET? |
| 02:55.39 | prpplague | T0mW: but didn't get a chance to test it |
| 02:55.45 | prpplague | T0mW: yea |
| 02:55.54 | T0mW | ok, I'm not surprised then |
| 02:56.14 | prpplague | T0mW: just seems odd compared to the intel sa series |
| 02:56.58 | prpplague | T0mW: the sharp engineer is coming to the office tomorrow with a bdi2000 unit to do some tests |
| 02:57.14 | T0mW | if you look at Jtag, you'll see that he keeps a copy of the outgoing bitstring and shifts against that bitstring. There is an input bitstring that he also keeps. The twain shall never meet. They are autonomous bitstrings. |
| 02:57.58 | T0mW | e.g. an out_bitstring to TDI and an in_bitstring from TDO |
| 02:58.10 | prpplague | T0mW: yea, same with jflash |
| 02:58.17 | T0mW | I thought that was curious, but you just explained why to me. |
| 02:59.43 | prpplague | T0mW: alot of it is starting to make sense, its just that i need a few last details to "push me over the edge" |
| 02:59.51 | T0mW | it must be we presume that there is a shift register bit and a latch bit (two flip/flops) at each stage of the chain. I guess there isn't, there is only one flop at each pin. |
| 03:00.58 | T0mW | kind of like musical chairs, when the shifting stops, theres your bit. X number of clocks of shifting causes the internal JTAG sequencer to present the bit to the pin. |
| 03:01.08 | prpplague | yep |
| 03:01.42 | prpplague | fun fun |
| 03:01.55 | T0mW | yeah, but, how would you expect the D0_en to keep it's value each time you send 507 bits out into TDI ??? |
| 03:02.02 | T0mW | that does not make sense, |
| 03:02.03 | T0mW | . |
| 03:03.32 | prpplague | T0mW: agreed |
| 03:03.53 | T0mW | what you are reading back via TDO prolly has to be taken into context of the data validity. You would only be interested in the INPUT bit states being read from TDO as you don't know what those states are going to be (they're inputs after all), your output bits & enable bits data would be meaningless as you already have that info. |
| 03:04.24 | T0mW | after all, you were the one who set the output & enable bits, therefore you know what state they should be in? |
| 03:04.59 | T0mW | IIAC, you are expecting to "see" the same bits shifted back from TDO that you last sent in via TDI ??? |
| 03:05.02 | prpplague | T0mW: agreed, just takes a little getting used too, + the fact the sharp engineer was confused as well |
| 03:05.33 | prpplague | T0mW: yea |
| 03:05.38 | T0mW | prpplague: *that* does not surprise me: that the field engineer is confused! 8O |
| 03:06.01 | prpplague | hehe |
| 03:06.29 | T0mW | prpplague: most of these guys do field work as the couldn't qualify to land a job doing design work!!! |
| 03:06.33 | prpplague | T0mW: sounds sick, but i'm really glad about these issues, its realy providing a good understanding |
| 03:06.38 | prpplague | T0mW: hehe |
| 03:06.59 | T0mW | I am too, it is knowledge you can bank on. usefull knowledge |
| 03:07.40 | prpplague | yea |
| 03:07.52 | T0mW | although, I would just rather use Jtag for now and keep the bit-level understanding to something more nebulous than to know which edge of TCK is the active one... :( |
| 03:08.09 | T0mW | heh |
| 03:08.09 | prpplague | hehe |
| 03:08.26 | prpplague | T0mW: call me a freak but i love the low level stuff |
| 03:08.44 | T0mW | Dave, you have to stop fuc^H^H^Hscrewing around, get your work done! |
| 03:09.15 | prpplague | T0mW: hehe, thats the best part about the new job, this is my work |
| 03:09.40 | T0mW | prpplague: I told myself that this evening: "Tom, leave the Jtag problem of the LPD board alone, you have to get the LCD controller code written and the LCD running". |
| 03:09.49 | prpplague | T0mW: my boss is a EE and, his directive was "don't come back until we can write code backwards and forwards using jtag" |
| 03:10.02 | T0mW | :P |
| 03:10.36 | T0mW | ~lart prpplague's boss |
| 03:11.15 | prpplague | hehe, my new boss rocks |
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