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| 12:31.01 | larsc | pcercuei: yes, happy new year. |
| 12:31.09 | larsc | I'm having trouble with your watchdog driver |
| 12:31.25 | larsc | the system reboots after a while even though the watchdog is not enabled |
| 12:33.15 | pcercuei | the upstream version? |
| 12:33.21 | larsc | yes |
| 12:34.26 | pcercuei | and it doesn't happen when the watchdog module is not loaded? |
| 12:34.38 | larsc | yes |
| 12:35.34 | pcercuei | we have a couple of changes here: https://github.com/gcwnow/linux/commits/jz-3.18/drivers/watchdog/jz4740_wdt.c |
| 12:36.14 | pcercuei | but that means you need a "wdt" clock |
| 12:46.57 | larsc | hm, looks as if something actually does enable the wdt |
| 12:47.16 | larsc | and once it is enabled the gpios keyboard doesn't work anymore, strange |
| 12:47.28 | pcercuei | huh |
| 12:53.54 | larsc | does gmenu2x has any watchdog code? |
| 12:56.50 | mth | no, we have a watchdog daemon |
| 13:02.38 | larsc | I really wonder why enabling the watchdog kills the gpios |
| 13:03.20 | mth | the watchdog doesn't use any pins, so that's probably not where the interference is |
| 13:03.27 | mth | maybe it messes with the wrong clock? |
| 13:03.47 | mth | or an interrupt? |
| 13:04.02 | larsc | it looks like gpio_get_value() is still correct, but it doesn't generate any interrupts anymore |
| 13:05.56 | larsc | actually it seems to kill the timer interrupt |
| 13:26.06 | larsc | if I remove the 'writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);' I still get the timer interrupts |
| 13:26.12 | larsc | otherwise they stop |
| 13:27.07 | larsc | strangely enough writing 0 to it again doesnt fix the issue |
| 13:28.12 | pcercuei | if you write 0x1, you write 0 to the upper 30 bits |
| 13:28.26 | pcercuei | is there anything in there? |
| 13:29.55 | larsc | not according to the datasheet |
| 13:33.30 | larsc | even if I replace the writeb(0x1, with writeb(0x0 it continuous to work |
| 13:39.37 | larsc | hm, switched things around to first setup the watchdog and then enable the watchdog clock in the tcu and things seem to work |
| 13:46.29 | larsc | only looked like it |
| 13:46.31 | larsc | really strange |
| 13:47.39 | pcercuei | we don't have those problems with the watchdog on jz4770 |
| 13:48.02 | pcercuei | so that's indeed strange |
| 13:57.27 | larsc | hm, does the watchdog timer also generate an interrupt? |
| 13:59.32 | pcercuei | no |
| 13:59.49 | pcercuei | that wouldn't make sense |
| 14:01.41 | larsc | it wouldn't |
| 14:01.52 | larsc | but right now the whole thing doesn't make sense |
| 14:02.09 | pcercuei | disable devicetree :p |
| 14:03.13 | larsc | this is plain mainline |
| 14:20.41 | mth | the Ben has a matrix keyboard, right? |
| 14:20.52 | mth | wouldn't that be polled on a timer rather than have GPIO interrupts? |
| 14:23.06 | larsc | both |
| 14:24.37 | larsc | it looks as if for whatever reason tcu0 channel just stops |
| 14:25.45 | mth | the watchdog timer stop is in the same register as the tcu timer stop flags, but the code looks fine |
| 14:25.59 | mth | jz4740_timer_enable_watchdog |
| 14:26.36 | larsc | I double checked that already, in the register it is still enabled |
| 14:26.48 | larsc | also just calling jz4740_timer_enable_watchdog() doesn't do anything |
| 14:27.16 | larsc | problems only start once the watchdog is enabled in the watchdog core |
| 14:28.40 | larsc | if I change the timer code to not use tcu0 everything is fine |
| 14:35.54 | larsc | are you using the watchdog on the dingoo? |
| 14:36.25 | pcercuei | we didn't update the kernel for a long time |
| 14:38.55 | larsc | which tcu channels are used for pwm on the dingoo? |
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| 14:41.18 | pcercuei | PWM7 for the backlight |
| 15:00.09 | larsc | maybe they just forgot to tell us that the wdt hijacks tcu0 |
| 15:02.16 | larsc | pcercuei: so, tomorrow morning 8 o'clock? ;) |
| 15:02.31 | pcercuei | probably not 8 o'clock |
| 15:04.34 | larsc | lots of work to do |
| 15:06.16 | pcercuei | it'll take time to even read the emails |
| 15:06.35 | larsc | all the ez posts |
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